MEAM.Design - ATmega32 programming - Timers/Counters - Timer 4 Configuration Details
Timer 4 is a 10-bit free-running timer with three independent output compare units, extensive PWM support, and a phased-locked-loop capable of clock speeds of up to 64 MHz. The output compare pins are OC4A, OC4B, and OC4D, which are multiplexed to C7, B6, and D7, along with optional inverted outputs on C6, B5, and D6.
Important Registers
| TCNT4 | lower 8 bits of timer/counter 4 value |
| TC4H | timer/counter 4 temporary high byte for A,B,C,D channels |
| TCCR4A-E | timer/counter 4 control registers A, B, C, D and E |
| OCR4A-D | timer/counter 4 output compare registers A,B,C,D (lower 8 bits) |
| TIMSK4 | timer/counter 4 interrupt control |
| TIFR4 | timer/counter 4 interrupt flags |
| DT4 | timer/counter 4 dead-time value |
Clock Source - The default clock source for Timer 4 is the system clock (to achieve clock speeds greater than the system clock, you will need to enable and use the PLL - see the datasheet). You can set the prescaler by modifying CS40, CS41, CS42, and CS43 bits in TCCR4B:
| TCCR4B: CS43 | TCCR4B: CS42 | TCCR4B: CS41 | TCCR4B: CS40 | |
| 0 | 0 | 0 | 0 | OFF |
| 0 | 0 | 0 | 1 | /1 |
| 0 | 0 | 1 | 0 | /2 |
| 0 | 0 | 1 | 1 | /4 |
| 0 | 1 | 0 | 0 | /8 |
| 0 | 1 | 0 | 1 | /16 |
| ... | ... | ... | ... | (you get the idea) |
| 1 | 1 | 1 | 1 | /16384 |
Timer Modes (Waveform Generation) - The timer waveform is controlled by setting WGM40 and WGM41 bits in TCCR4D. The two primary options are to have the timer count up to a value then reset to 0x00 (sawtooth, or UP mode), or to count up to a value, then count back down to 0x00 (triangle wave, or UP/DOWN mode).
| TCCR4D: WGM41 | TCCR4D: WGM40 | |
| 0 | 0 | UP to OCR4C |
| 0 | 1 | UP to OCR4C, DOWN to 0x00 |
Timer TOP Value - The TOP value for Timer 4 (when it will either reset to 0x00 or begin counting down, depending upon the mode) is set in OCR4C.
If using Timer 4 as an 8-bit timer (max of 255), you can set this value by writing directly to OCR4C. If you'd like to use 10-bit resolution (max of 1023), then you will need to write the high byte to the temporary high-byte register (TC4H) immediately before writing the low byte to OCR4C. Note that the minimum value for OCR4C is 3. Any value less than 3 will automatically be changed to 3.
Note: You can eek out a bit more resolution for output compare by enabling the ENHC4 bit in the TCCR4E register, which turns on "Enhanced Compare/PWM Mode". In this mode, you can trigger the change on the edge of the clock signal, effectively adding an extra bit of resolution. See section 15.6.2 of the datasheet for the particulars of operation.
Channel A Compare Output (OC4A) Options - OC4A is multiplexed onto C7, which means that you must first set bit 7 of DDRC to enable output. The behavior of the OC4A output is then controlled by setting certain bits within the TCCR4A register:
| TCCR4A: PWM4A | TCCR4A: COM4A1 | TCCR4A: COM4A0 | |
| X | 0 | 0 | disconnected |
| 0 | 0 | 1 | TOGGLE at compare with OCR4A |
| 0 | 1 | 0 | CLEAR at compare with OCR4A |
| 0 | 1 | 1 | SET at compare with OCR4A |
| 1 | 1 | 0 | CLEAR at compare with OCR4A, SET at 0x00 |
| 1 | 1 | 1 | SET at compare with OCR4A, CLEAR at 0x00 |
To set a compare value (OCR4A) greater than 255, you will need to follow the same procedure used to set the TOP value by writing the high byte to TC4H immediately before setting the low byte to OCR4A.
Channel B Compare Output (OC4B) Options - OC4B is multiplexed onto B6, which means that you must first set bit 6 of DDRB to enable output. The behavior of the OC4B output is then controlled by setting certain bits within the TCCR4A register:
| TCCR4A: PWM4B | TCCR4A: COM4B1 | TCCR4A: COM4B0 | |
| X | 0 | 0 | disconnected |
| 0 | 0 | 1 | TOGGLE at compare with OCR4B |
| 0 | 1 | 0 | CLEAR at compare with OCR4B |
| 0 | 1 | 1 | SET at compare with OCR4B |
| 1 | 1 | 0 | CLEAR at compare with OCR4B, SET at 0x00 |
| 1 | 1 | 1 | SET at compare with OCR4B, CLEAR at 0x00 |
To set a compare value (OCR4B) greater than 255, you will need to follow the same procedure used to set the TOP value by writing the high byte to TC4H immediately before setting the low byte to OCR4B.
Channel D Compare Output (OC4D) Options - OC4D is multiplexed onto D7, which means that you must first set bit 7 of DDRD to enable output. The behavior of the OC4D output is then controlled by setting certain bits within the TCCR4C register:
| TCCR4C: PWM4D | TCCR4C: COM4D1 | TCCR4C: COM4D0 | |
| X | 0 | 0 | disconnected |
| 0 | 0 | 1 | TOGGLE at compare with OCR4D |
| 0 | 1 | 0 | CLEAR at compare with OCR4D |
| 0 | 1 | 1 | SET at compare with OCR4D |
| 1 | 1 | 0 | CLEAR at compare with OCR4D, SET at 0x00 |
| 1 | 1 | 1 | SET at compare with OCR4D, CLEAR at 0x00 |
To set a compare value (OCR4D) greater than 255, you will need to follow the same procedure used to set the TOP value by writing the high byte to TC4H immediately before setting the low byte to OCR4D.
Flags - There are four flags within the TIFR4 register that can be used to monitor Timer 4:
| TIFR4 : OCF4A | set when TCNT4 matches OCR4A |
| TIFR4 : OCF4B | set when TCNT4 matches OCR4B |
| TIFR4 : OCF4D | set when TCNT4 matches OCR4D |
| TIFR4 : TOV4 | set whenever TCNT4 returns to 0x0000 |
These can be cleared by writing a logic 1 to the register bit (e.g.: set(TIFR4,TOV4) to clear the overflow flag)
Interrupts - There are four interrupt vectors associated with Timer 4:
To call an interrupt whenever Timer 4 returns to 0x00, set the TIMSK4 : TOIE4 bit, and write a handler for the TIMER4_OVF interrupt vector.
To call an interrupt whenever (TCNT4 matches OCR4A), set the TIMSK4 : OCIE4A bit, and write a handler for the TIMER4_COMPA interrupt vector.
To call an interrupt whenever (TCNT4 matches OCR4B), set the TIMSK4 : OCIE4B bit, and write a handler for the TIMER4_COMPB interrupt vector.
To call an interrupt whenever (TCNT4 matches OCR4D), set the TIMSK4 : OCIE4D bit, and write a handler for the TIMER4_COMPD interrupt vector.
And do not forget to enable global interrupts, as discussed here.
Note that entering any of these interrupts will automatically clear the coresponding TIFR4 flag.